The article focuses on methods for reducing high inductance in power supply circuits using one of the IC substrate topologies with a high-speed interface as an example. The interface in question operates at a speed of 28.25 Gbit/s and imposes strict requirements on the parameters of the power supply inductance. The presented solutions are aimed at ensuring low values of power supply inductance in conditions of high layout density and power integrity requirements for modern data transfer interfaces.
Keywords: power supply inductor, power system, low noise power supply, power supply impedance, analog power supply, serial interface, high speed interface, organic substrate, IC packaging